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Design Verification Engineer

Canvendor

Santa Clara, USA, United States of America

Not Disclosed

2 - 7 Years

Full Time - Permanent

Views:97

Applicants:0

Posted on 21 Dec, 2025

In Office

Job Description | Responsibilities

  • Experience in IP/SOC verification

  • Worked on full project cycles including tape-outs

  • Strong in debugging design & verification failures

  • Proficient in Verilog, SystemVerilog, UVM

  • Skills- functional coverage development & closure

  • Developed assertions and checkers

  • Testcase planning and creation

  • Practical knowledge of PCIe, Ethernet, CXL, USB, CAN

Overview

  • Industry - Management Consulting
  • Functional Area - IT Hardware EDA / VLSI / ASIC / Chip Designing / Networking / Remote Sensing
  • Job Role - Other Top Management IT Hardware EDA / VLSI / ASIC / Chip Designing / Networking / Remote Sensing
  • Employment type - Full Time - Permanent
  • Work Mode - In Office
  • Open To Hire - Other Industry

Qualifications

  • Any Graduate - Any Specialization
  • Any Post Graduate - Any Specialization
  • Any Doctorate - Any Specialization

Job Related Keywords

Design Verification Engineer IP/SOC Verification Tape-out Debugging Verilog SystemVerilog UVM Functional Coverage