Design Verification Engineer
Canvendor
Santa Clara, USA, United States of America
Not Disclosed
2 - 7 Years
Full Time - Permanent
Views:97
Applicants:0
Posted on 21 Dec, 2025
Job Description | Responsibilities
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Experience in IP/SOC verification
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Worked on full project cycles including tape-outs
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Strong in debugging design & verification failures
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Proficient in Verilog, SystemVerilog, UVM
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Skills- functional coverage development & closure
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Developed assertions and checkers
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Testcase planning and creation
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Practical knowledge of PCIe, Ethernet, CXL, USB, CAN
Overview
- Industry - Management Consulting
- Functional Area - IT Hardware EDA / VLSI / ASIC / Chip Designing / Networking / Remote Sensing
- Job Role - Other Top Management IT Hardware EDA / VLSI / ASIC / Chip Designing / Networking / Remote Sensing
- Employment type - Full Time - Permanent
- Work Mode - In Office
- Open To Hire - Other Industry
Qualifications
- Any Graduate - Any Specialization
- Any Post Graduate - Any Specialization
- Any Doctorate - Any Specialization