Santa Clara, USA, United States of America
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Posted on 21 Dec, 2025
Experience in IP/SOC verification
Worked on full project cycles including tape-outs
Strong in debugging design & verification failures
Proficient in Verilog, SystemVerilog, UVM
Skills- functional coverage development & closure
Developed assertions and checkers
Testcase planning and creation
Practical knowledge of PCIe, Ethernet, CXL, USB, CAN