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Posted on 31 Dec, 2025
- Industry - IT - INFORMATION TECHNOLOGY
- Functional Area - Research / R&D - Engineering / Environmental / Space
- Job Role - Design Engineer
- Employment type - Full Time - Permanent
- Work Mode - In Office
- Develop and execute formal verification plans for digital blocks and SoC integrations using SystemVerilog and UVM methodologies.
- Implement directed and constrained?random testbenches, stimulus generators, and assertions to validate RTL against specifications.
- Any Graduate - Any Specialization
- Any Post Graduate - Any Specialization
- Any Doctorate - Any Specialization
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