Memory Layout Engineer

• Experience with 16nm to 3nm nodes and FinFET

• Skilled in memory compiler and layout optimization

• Strong in routing congestion and physical verification (DRC, LVS, ERC, etc.)

• Knowledge of analog layout impact on performance and area

• Proficient in Cadence, Mentor tools, VirtuosoXL on Linux

• Leadership in mentoring and quality delivery

Overview

• Industry - Management Consulting
• Functional Area - IT Hardware EDA / VLSI / ASIC / Chip Designing / Networking / Remote Sensing
• Job Role - IC Layout Engineer
• Employment type - Full Time - Permanent
• Work Mode - In Office
• Open To Hire - Other Industry

Qualifications

• Any Graduate - Any Specialization
• Any Post Graduate - Any Specialization
• Any Doctorate - Any Specialization

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