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Posted on 28 May, 2025
In Office
Job Description | Responsibilities
- Architect and develop UVM-based testbenches for PCIe IP or SoCs
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Execute verification plans including PCIe protocol compliance (LTSSM, BARs, DLLP/TLP, etc.)
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Perform coverage-driven and assertion-based verification
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Work with RTL, system, and post-silicon teams to debug and resolve issues
Overview
- Industry - IT - Consulting Services / Advisory Services
- Functional Area - IT Hardware EDA / VLSI / ASIC / Chip Designing / Networking / Remote Sensing
- Job Role - Hardware Design Engineer
- Employment type - Full Time - Permanent
- Work Mode - In Office
- Open To Hire - Differently Abled, Retired, Defence Veteran, Government Employees, Self Employed
Qualifications
- Any Graduate - Any Specialization
- Any Post Graduate - Any Specialization
- Any Doctorate - Any Specialization
Job Related Keywords
SystemVerilog
UVM
PCIe Gen5
PCIe Gen6
SoC Verification
ASIC DV
VCS
Questa