OTTAWA, Canada
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Applicants:3
Posted on 15 Nov, 2025
Take ownership of an assigned analog block and deliver it for use in Marvell’s IP portfolio.
Evaluate and compare circuit topologies, considering performance, power, and area trade-offs.
Perform schematic capture and layout using Cadence Virtuoso.
Run schematic-level and post-layout simulations to analyze, optimize, and validate performance.