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Verification Engineer (I3C_MASTER)
MAXVY Technologies Pvt. Ltd.
Bengaluru / Bangalore
Not Disclosed
1 - 5 Years
Full Time - Permanent
Views:10
Applicants:2
Posted on 28 Aug, 2026
In Office
Job Description | Responsibilities
- Develop SystemVerilog/UVM verification environments.
- Create test plans, sequences, assertions, and testbenches.
- Verify APB, I2C, and I3C protocols.
- Run simulations, analyze failures, and debug issues.
- Drive functional coverage and verification closure.
Overview
- Industry - Electronic Manufacturing & Equipments
- Job Role - Verification Engineer (I3C_MASTER)
- Employment type - Full Time - Permanent
- Work Mode - In Office
Qualifications
- Any Graduate - Any Specialization
- Any Post Graduate - Any Specialization
- Any Doctorate - Any Specialization
Job Related Keywords
SystemVerilog
UVM
I3C
I2C
APB
Testbench
Assertions
Functional Coverage
RTL Verification