Synthesis Engineer

• Perform RTL synthesis using tools like Synopsys Design Compiler, Fusion Compiler, or Cadence Genus.
• Develop and validate timing constraints (SDC) for complex designs with multiple clock domains.
• Execute Static Timing Analysis (STA) using PrimeTime or Tempus to ensure timing closure .
• Automate synthesis and STA flows using TCL, Perl, or Python.

Overview

• Industry - Electronic Manufacturing & Equipments
• Job Role - ENGINEERING
• Employment type - Full Time - Permanent
• Work Mode - In Office

Qualifications

• Any Graduate - Any Specialization
• Any Post Graduate - Any Specialization
• Any Doctorate - Any Specialization

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