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STA/Synthesis (Staff)
Connectpro Management Consultants Pvt. Ltd.
Chennai
Not Disclosed
10 - 14 Years
Full Time
Views:200
Applicants:0
Posted on 28 Nov, 2024
In Office
Job Description | Responsibilities
- Synthesis, Static Timing Analysis and LEC of SoC/Cores
- Full chip and block level timing closure, IO budgeting for blocks
- Logical equivalence check between RTL to Netlist and Netlist to Netlist
- ECO timing flow
Overview
- Industry - HR, HUMAN RESOURCES
- Functional Area - Other
- Job Role - Other
- Employment type - Full Time
- Work Mode - In Office
Qualifications
- Any Graduate - Any Specialization
- Any Post Graduate - Any Specialization
- Any Doctorate - Any Specialization
Job Related Keywords
TCL and Perl
clock gating
power gating and MV designs