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Posted on 31 Dec, 2025
Overview
- Industry - IT - INFORMATION TECHNOLOGY
- Functional Area - IT Hardware EDA / VLSI / ASIC / Chip Designing / Networking / Remote Sensing
- Job Role - Other IT Hardware - EDA / VLSI / ASIC / Chip Designing
- Employment type - Full Time - Permanent
- Work Mode - In Office
Job Description | Role and Responsibilities
Perform full-chip and block-level Static Timing Analysis (STA)
Setup and analyze timing constraints (SDC) including clocks, I/O constraints, exceptions
Perform timing closure for different modes and corners (MCMM)
Identify and debug setup, hold, recovery, and removal violations
Handle ECOs related to timing fixes
Candidate Profile | Who Can Apply
Education
- Any Graduate - Any Specialization
- Any Post Graduate - Any Specialization
- Any Doctorate - Any Specialization
Job Related Keywords
About Employer
Contact Details
Email - hr@gigaopsglobal.com,
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