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RTL Engineers (STA/Synthesis)

MAXVY Technologies Pvt. Ltd.

Bengaluru / Bangalore

Not Disclosed

5 - 8 Years

Full Time - Permanent

Views:10

Applicants:0

Posted on 28 Aug, 2026

In Office

Job Description | Responsibilities

  • Own RTL synthesis, timing constraints, STA, and ECO flows.
  • Perform block/chip-level timing analysis and closure.
  • Develop SDC constraints and optimize timing, area, and power.
  • Collaborate with RTL, PD, and DFT teams to resolve issues.
  • Automate design-closure tasks using scripting tools.

Overview

  • Industry - Electronic Manufacturing & Equipments
  • Job Role - RTL Engineer (STA/Synthesis)
  • Employment type - Full Time - Permanent
  • Work Mode - In Office

Qualifications

  • Any Graduate - Any Specialization
  • Any Post Graduate - Any Specialization
  • Any Doctorate - Any Specialization

Job Related Keywords

RTL Synthesis STA Timing Closure SDC ECO PrimeTime Design Compiler Tcl/Python

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