SANTA CLARA, USA, United States of America
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Applicants:8
Posted on 15 Nov, 2025
Work with RTL engineers to verify Verilog-based designs using SystemVerilog.
Develop and debug testbenches; run simulations using Synopsys VCS or equivalent tools.
Debug design issues and iterate until verification requirements are met.
Collaborate with DFT engineers and cross-functional chip design teams.