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Design Verification Engineer
Connectpro Management Consultants Pvt. Ltd.
Bengaluru / Bangalore
Not Disclosed
5 - 19 Years
Full Time - Permanent
Views:101
Applicants:0
Posted on 2 Jun, 2025
In Office
Job Description | Responsibilities
- Good understanding of ASIC verification concepts and techniques.
- Very good knowledge of Verilog/System Verilog and UVM.
- Experience and knowledge in Verification of IP / SoCs related to different applications.
- Good Knowledge in Power aware verification and Gate level verification is preferable
Overview
- Industry - HR, HUMAN RESOURCES
- Functional Area - Other
- Job Role - Other
- Employment type - Full Time - Permanent
- Work Mode - In Office
Qualifications
- Any Graduate - Any Specialization
- Any Post Graduate - Any Specialization
- Any Doctorate - Any Specialization
Job Related Keywords
Full-chip Verification requirements
Design / Designing
Design Verification
Engineer
Design Verification Engineer
Verilog and UVM
